Monolithic semiconductor switching device

ABSTRACT

An electrical circuit device made in integrated monolithic form has low level operating characteristics of a MOS device and high level operating characteristics of a Triac. The structure includes two double diffused MOS transistors which have merged drain regions. At higher voltage and current levels a lateral Triac structure is triggered by the MOS devices. Alternatively, separate terminal contacts can be made to the P and N regions comprising the MOS transistor source and channel regions with the Triac triggered conventionally by an externally applied control voltage.

BACKGROUND OF THE INVENTION

This invention relates generally to semiconductor circuits and devices,and more particularly the invention relates to an integrated circuitdevice having current dependent properties.

The metal oxide silicon (MOS) field effect transistor and themultijunction silicon controlled rectifier and Triac are knownsemiconductor devices which have current switching applications. The MOStransistor generally operates at lower voltages and current levels andcan be used in linear applications. One form of MOS transistor is thedouble diffused device in which a very short channel region is definedby diffusing a region of one conductivity type in a substrate ofopposite conductivity type and then diffusing a region of oppositeconductivity type in the first region. The silicon controlled rectifier(SCR) or Triac is normally employed for higher voltage and currentswitching applications. The MOS transistor employs a field effectchannel created by the application of a gate voltage, while the SCRtypically is turned on by forward biasing a PN junction which rendersthe device conductive. The Triac is similar to the SCR but provides fullwave switching.

SUMMARY OF THE INVENTION

An object of this invention is a new and improved current switchingdevice.

Another object of the invention is an electrical circuit device whichhas the characteristics of an MOS transistor and of a full wave siliconswitch.

Still another object of the invention is a monolithic semiconductordevice having operational characteristics which are current dependent.

A feature of the invention is a monolithic semiconductor deviceincluding two merged double diffused MOS transistors.

Briefly, a device in accordance with the invention comprises asemiconductor body having at least one major surface and a regionadjacent to the surface of one conductivity. First and second spacedregions of opposite conductivity type are formed in the body region andabutting the major surface. Third and fourth regions of the oneconductivity type are formed in the first and second regions,respectively, abutting the major surface and defining first and secondchannel regions in the first and second regions, respectively. A layerof insulation is formed on the major surface and an ohmic contact isformed on the layer of insulation and adjacent to the first and secondgate regions. An ohmic contact is made to the first and third regions,and an ohmic contact is made to the second and fourth regions. An ohmiccontact between the first and third regions and between the second andfourth regions may be facilitated by a separate diffusion of the sameconductivity type as regions one and two adjacent to regions one andtwo. This diffusion is normally performed prior to diffusion of regionsone and two, with a separate masking operation.

The first and third regions cooperatively function with the body regionas a first double diffused MOS transistor, and the second and fourthregions cooperatively function with the body region as a second doublediffused MOS transistor. The body region functions as a merged drain ofthe two transistors. A fifth diffused region of the same conductivitytype as the body region can be formed in the body region between thefirst and second diffused regions.

At lower operating voltages and currents, the device functions asserially connected MOS transistors having merged drain regions, while athigher voltages and operating currents the device functions as a fullwave silicon switch.

The invention and objects and features thereof will be more readilyapparent from the following detailed description and appended claimswhen taken with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section view of a conventional double diffused MOStransistor.

FIG. 2 is a cross section view of one embodiment of a switching devicein accordance with the present invention.

FIG. 3A and FIG. 3B are an electrical schematic and voltage-currentcharacteristics, respectively, of the device of FIG. 2 at loweroperating voltages.

FIGS. 4A and 4B are an electrical schematic and voltage-currentcharacteristics, respectively, of the device of FIG. 2 operated athigher voltage level.

FIG. 5A .[.and.]..Iadd., .Iaddend.FIG. 5B, .Iadd.and FIG. 5C.Iaddend.are an electrical schematic and voltage-currentcharacteristics, respectively, of the device of FIG. 2 operated at stillhigher voltages.

FIG. 6 is the doping profile along the silicon surface of one embodimentof the device of FIG. 2.

FIG. 7 is a cross section view of another embodiment of a switch devicein accordance with the present invention.

FIGS. 8A, 8B, 8C illustrate schematically several applications of thedevice of FIG. 7.

FIGS. 9-13 are cross section views of other embodiments of devices inaccordance with the invention.

FIG. 14 is an electrical schematic of the device shown in FIGS. 12 and13.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENT

Referring now to the drawings, FIG. 1 is a cross section view of aconventional double diffused MOS transistor (DMOS) formed in a lightlydoped (N-) semiconductor body 10. The device includes a first P+diffused region 12a, a second P diffused region 12 overlapping a portionof region 12a, a third N+ diffused region 14 formed in the P region 12with all three regions being adjacent to a major surface of thesemiconductor body 10. The N+ region 14 comprises the source of thetransistor, and the portion 16 of P region 12 adjacent to the majorsurface and between the N+ region 14 and the N- body 10 comprises thetransistor channel. An N+ diffused region 18 spaced from the first tworegions along with the adjacent N- body region comprises the transistordrain. A silicon oxide layer 20 is formed on the major surface of thesemiconductor body 10 with a metallic ohmic contact 22 made to regions12, 12a and 14, a metallic ohmic contact 24 made to the drain region 18,and a metallic layer for the gate electrode 26 formed on the layer ofinsulation 20 above the channel region 16.

The device functions as a typical MOS transistor with a short channelregion provided by the double diffused structure. However, due to the PNjunction between region 12 and the body 10, the DMOS device isinherently asymmetrical; that is, the source and drain terminals are notinterchangeable. This asymmetry can be a problem in many circuitapplications, and a device in accordance with the present inventionovercomes this limitation.

Referring now to FIG. 2, one embodiment of a device in accordance withthe present invention is illustrated in cross section. The device iseffectively two DMOS devices shown generally at 30 and 32 integrated ina monolithic semiconductor body 36 with merged drain regions. The DMOStransistor 30 comprises a source N+ region 33, a channel region 34formed in P region 35 and a drain comprising the N- semiconductor body36 and the N+ diffused region 37. DMOS transistor 32 comprises an N+source 38, a P channel region 39 formed in P region 40, and a draincomprising the N- body 36 and the N+ diffused region 37. Regions 35a and40a again are P+ diffused regions designed to facilitate ohmic contactto the P channel regions 35 and 40. One input-output (I/O) contact 42 ismade to regions 33, 35 and 35a, a second I/O contact 44 is made toregions 38, 40 and 40a, and a gate electrode 46 is formed on the siliconoxide layer 48 above the channel regions 34, 39.

Due to the symmetrical construction of the device as shown in FIG. 2,the device has symmetry of operation, i.e. the two I/O contacts areinterchangeable. Importantly, the operational characteristics of thisdevice change with the operating voltage and current levels.

FIG. 3A is an electrical schematic of the device in FIG. 2 operated atlow voltage and current levels (e.g. less than one volt across thedevice, gate voltage of a few volts above the threshold voltage), andFIG. 3B is the current-voltage operating characteristics of the deviceof FIG. 3A. In FIG. 3A the two DMOS transistors 30 and 32 are shownserially connected with the I/O terminals 42, 44 connected to the sourceregions of transistors 30 and 32, respectively, and gate terminal 46controlling the gates of both transistors. Diode 52 formed by P region35 and the N- body 36 is connected in parallel with transistor 30, anddiode 50 formed by P region 40 and the N- body 36 is connected inparallel with transistor 32. Thus, since the two diodes are provided inseries opposition, the device in accordance with the present inventionis symmetrical at lower voltage and current operation. FIG. 3B is a plotof current vs. voltage for low-level operation wherein the devicefunction in accordance with the circuit illustrated in FIG. 3A.

For applied voltages greater than approximately 1.5 volts (gate voltageof a few volts above the threshold voltage), holes are injected intosemiconductor body 36 by the plus voltage on P regions 40 and 40a, withP regions 40 and 40a and 35 and 35a functioning with the N-semiconductor body 36 as a PNP transistor 60 connected as shown in FIG.4A. Referring to the plot of voltage vs. current in FIG. 4B, thetransconductance or gain of the device shows a sharp increase. However,the device remains symmetrical. The increase in transconductance ordevice gain can be attributed to the injected holes from regions 40 and40a which pass through body 36 and are collected at regions 35 and 35a.These collected holes contribute to the total device current (which ismeasured externally) and thus increase the transconductance or devicegain. Some of the injected holes recombine with majority carriers in theN- region while the remaining injected holes are collected at regions 35and 35a. Thus, applied voltages greater than approximately 1.5 voltscause the lateral PNP transistor to turn on. The current contributed bythis device explains the increase in overall device gain as demonstratedby the plot in FIG. 4B. In this mode of operation two parallelconduction paths are provided in the device, electron flow through thesurface DMOS devices and hole current through the lateral PNPtransistor. The overall device current is the sum of the DMOS electroncurrent and the injected hole current.

By increasing current flow through the device by increasing gatevoltage, for example, an applied voltage of +2 volts on one I/O terminaland a +10 volt gate potential, the device assumes an electrical andequivalent electrical schematic as demonstrated in FIGS. 5A and 5B, withthe other I/O terminal grounded. In this mode of operation the deviceassumes the characteristics of a Triac with switching action to a lowresistance device, similar to that observed in PNPN four layerstructures. The structure shown in FIG. 2 can be viewed as a lateralNPNPN structure, or a symmetrical PNPN arrangement, between the two I/Oterminals. As illustrated in FIG. 5A, an NPN transistor 62 formed byregions 33, 35 and 36 of the structure in FIG. 2, is added to thecircuit of FIG. .[.4B.]. .Iadd.4A .Iaddend.with transistor 62 shuntingDMOS transistor 30. Both electrons and holes continue to contribute tothe overall device current, however, the holes collected by the P region35 (FIG. 2) flow through a relatively high resistance before reachingthe I/O contact 42. This resistance is denoted 64 in the schematic ofFIG. 5A, and is physically analogous to the base resistance in a bipolartransistor and is an inherent part of the DMOS structure. The resistanceis a distributed resistor and holes are collected all along its length.The voltage drop along the resistor will tend to forward bias the PN+junction (region 35, 33) which is the base-emitter junction of the NPNtransistor whose collector is the N- body 36. Once the voltagedifferential turns the NPN transistor on (at approximately 0.7 volts) aregenerative switching causes the four layer structure comprising thetwo bipolar transistors to switch to a low resistance state, which isillustrated in FIG. .[.5B.]. .Iadd.5C. .Iaddend.Transistors 60 and 62are equivalent to the arrangement of PNP and NPN devices used inconventional Triacs and SCRs.

It should be noted that the Triac or SCR is switched by applying atrigger voltage from an external source. While the device as illustratedin FIG. 2 is triggered to a low resistance state when the currentthrough the device is increased by increasing the gate voltage, thedevice can be made to operate as a conventional SCR by forward biasing ajunction. If separate ohmic contacts are formed to regions 35a and 33,externally forward biasing the P+N+ junction between regions 35a and 33will switch the device to its low resistance state. However, the deviceillustrated in FIG. 2 is switched to a low resistance mode by an MOSdevice in parallel with the Triac and not by forward biasing thejunction externally, as is found with the conventional Triacs and SCRs.At low current levels before the Triac fires, the MOS characteristics ofthe structure dominate. After firing the Triac, the device becomes a lowresistance device.

FIG. 6 illustrates the surface doping profile for one switch device inaccordance with the present invention. Absolute surface dopingconcentration is illustrated along the ordinate and distance across thedevice is illustrated along the abscissa. Relating the dopingconcentration to the device illustrated in cross section in FIG. 2, theN+ regions 33, 37 and 38 have a dopant concentration on the order of10²⁰ impurities per cubic centimeter. The P regions which comprise thechannel regions of the two DMOS transistors 34, 39 have a peak dopantconcentration on the order of 5×10¹⁶ impurities per cubic centimeter.The dopant concentration of the N- semiconductor body is on the order of10¹⁵ impurities per cubic centimeter.

In fabricating the device, P+ diffusions are first formed to facilitateohmic contact to the DMOS transistor channel regions. Then sequentialdiffusions of boron (P type) and phosphorus or arsenic (N type) are madeemploying conventional diffusion techniques to form the P and N+regions. Ion implantation may also be advantageously used to introducethe boron (P type) impurity for the channel region of the devices. Thegate oxidation is then formed over the channel regions, contact holesare made for the I/O contacts, metal is formed over the surface of thedevice and the metal pattern is defined by conventional photoresistmasking and etching techniques.

The maximum doping in the P region at the surface under the gate alongwith the gate oxide thickness and the oxide charge density determine theDMOS threshold voltage. The channel width largely determines the DMOStransconductance and on resistance. The channel width also affects theTriac trigger current because the Triac is triggered by a specificcurrent density flowing through the device. The DMOS properties arelargely independent of the channel length.

The channel doping profile determines directly the DMOS thresholdvoltage. In addition, the current density at which switching to the lowresistance mode of operation occurs is affected by this profile.

The doping level in the N- semiconductor body affects the devicebreakdown voltage, the DMOS on resistance and the lateral PNP transportefficiency.

The N+ drain region in the middle of the device is important in order toincrease the breakdown voltage. If this diffused region is not includeda parasitic P channel MOS transistor across the surface will reduce thebreakdown voltage to the field oxide threshold voltage which istypically 20 to 40 volts. In addition, this N+ region increases thelateral PNP transport efficiency. The lateral dimension of the N+ regionshould be minimized as it degrades the PNP transport efficiency.

Referring now to FIG. 7, several modifications to the device shown incross section in FIG. 2 are made. The same numerals are given to likeelements. The semiconductor body region 36 in this embodiment comprisesan epitaxial layer formed on a P- substrate 70. The structure maycomprise a plurality of switching devices with each device isolated bymeans of diffused P+ regions 72 and 74 which extend through theepitaxial layer 36 to the underlying substrate 70 and surround thedevice. However, it is noted that a P+ substrate collects injected holesthus delaying the turn-on of the Triac lateral structure. Experimentalresults indicate that depending upon device geometry 10% to 50% of theinjected holes are collected by the substrate before the Triac fires.While this does affect the efficiency of the device at higher voltageand current levels, the efficiency of the device is not affected at lowvoltage and current levels when all of the device current is carried bythe MOS transistors. By adding an N+ buried layer between the N-epitaxial layer and the P- substrate, a reduction in injected holescaptured by the substrate would be effected. Such buried layers arecommonly employed in commercial integrated circuits and are readilyacapted in standard production techniques. Additionally, dielectricisolation techniques can be employed instead of diffused isolation asshown in FIG. 7. By employing dielectric isolation the P- substrate ofFIG. 7 can be replaced with an insulator, and consequently injectedholes are not collected by the substrate. Alternatively, the P+ diffusedregions, 72, 74 can be replaced by a dielectric such as silicon oxide.

The N+ region 37 spaced from the two double diffused regions is notnecessary for low voltage. Triac operation and it can be eliminated ifthe device is not operated at high voltages. By eliminating this N+region, the base width of the lateral PNP transistor can be reduced,resulting in lower triggering currents for the Triac and lower onresistance for the DMOS device. However, as indicated above theelimination of the N+ regoin creates a parasitic PMOS transistor betweenthe two P diffused regions thus limiting the device breakdown voltage.

The separate ohmic contact made to the N+ region 37 as illustrated inFIG. 7 allows more versatility in operation of the device. The devicecan still be operated as a switching device as above described and asillustrated schematically in FIG. 8A. The N+ connection 78 can be leftfloating or can be connected to the +V potential applied to terminal.[.42.]. .Iadd.44.Iaddend.. By connecting the terminal to the +Vpotential, the DMOS characteristics will dominate up to a higher voltageand current level before the device becomes a low resistance switch.

Alternatively, as shown schematically in FIG. 8B the device can be usedas a standard DMOS transistor over its full operating range byconnecting terminals 42 and 44 together as the source, and the N+contact 78 becomes the drain.

In FIG. 8C, the device is used as a high level analog switch wherein atransducer 80 is driven at a high voltage with the transducer also usedas part of a receiver. In this application the Triac capability is usedwith the transmitter, and the single DMOS capability is used with areceiver. Such a circuit would have application in an ultrasonic imagingsystem, or other applications involving transmit-receive switching.

FIG. 9 is a cross section view of another embodiment of a device inaccordance with the present invention. In this embodiment the gatemetallization is split into two separate gate contacts 46-1 and 46-2.This structure allows separate control of the firing of the device inthe first and third quadrants of the device I-V characteristics. Whenthe terminal 44 is positive (the anode) gate 46-1 is used to trigger thedevice. When the terminal 42 is positive (the anode), gate 46-2 is usedto trigger the device. This configuration is useful in minimizing highoxide electric fields between the anode and the gate.

FIG. 10 is a cross section view of another embodiment of the device inaccordance with the present invention. In this embodiment a singledouble diffused region comprising the N+ region 33 and P region 35 isprovided along with a P+ diffused region 37. Contact 42 is made toregions 33 and 35, usually with the addition of P+ region 35a, a gatecontact 46-1 is made over oxide 48, and an ohmic contact 78 is made tothe P+ region 37. This structure forms an MOS controlled siliconcontrolled rectifier and operates in the same mode as the device of FIG.2 except that it is not symmetrical. Contact 78 must always be the anodeand contact 42 must always be the cathode. The device has high inputimpedance on the control electrode 46-1, and good isolation is providedbetween the control and signal paths.

FIG. 11 is a cross section view of another device in accordance with thepresent invention which also functions as an MOS controlled siliconcontrolled rectifier. Double diffused region 100 and 102 are formed inN- epitaxial layer 104, and anisotropic silicon etching is employed toform a V groove through the regions 100 and 102 into the epitaxial layer104. An oxide layer 106 is thermally grown or deposited in the V grooveand a gate contact 108 is formed thereover. An anode contact 110 is madeto the P+ substrate 105, the contacts 111 and 112 to the double diffusedregions are connected in parallel as the cathode, and contact 108 is thegate. In this device current flows vertically.

FIG. 12 and FIG. 13 are cross section views of a device similar to thedevice of FIG. 2 and in which an additional MOS transistor is added toachieve a turnoff capability. In FIG. 12 the added MOS transistor isprovided by a diffused P+ region 122 which is spaced from the P+ region35a with the N- substrate region therebetween functioning as a channelregion of an MOS transistor. The gate electrode to transistor 120 is theoff gate, and the gate electrode to the merged transistor 30 and 32 isthe on gate.

FIG. 13 is a similar structure in which the device is formed in an N-epitaxial layer 124 on a P- substrate 126 with P+ isolation regions 128diffused through the epitaxial layer 124. In this embodiment the addedtransistor 120 is isolated from the merged transistor structure andcomprises a double diffused MOS transistor (DMOS).

FIG. 14 is the equivalent electrical schematic of the devicesillustrated in FIG. 12 and FIG. 13 and is similar to the electricalschematic of FIG. 5A with the addition of the transistor 120 and offgate. When the off gate is turned on, the MOS transistor 120 effectivelyshorts out the base-emitter junction of the NPN transistor 62 thusbringing the transistor out of saturation. This causes the overalldevice to transfer from its low impedance regenerative condition and,provided the on gate is not turned on, will shut the device completelyoff thereby stopping anode current. This is a unique capability for aTriac type structure and is especially attractive because a highimpedance MOS input is used to turn the device off. In addition, an offswitch may be included on the anode (A) side of the device to enable itto be switched off when the anode and the cathode are reversed. Thismakes the overall device symmetric. Additionally, the transistor 120 maybe used as a variable resistor to electronically vary the current atwhich the device switches to a low impedance regenerative condition. Itwill be appreciated that in a junction isolated or dielectricallyisolated structure, the device in accordance with the present inventionmay be fabricated along side other components as technology infabricating the device is compatible with the fabrication of othersemiconductor devices.

The switching device in accordance with the present invention has anumber of applications including analog multiplexers with high current"boost" capability, high voltage display driving, telephone cross pointswitches, and in power control applications.

Thus, while the invention has been described with reference to specificembodiments and applications, the description is illustrative of theinvention and is not to be construed as limiting the invention. It willbe appreciated that various manufacturing techniques are known forfabricating the devices and equivalent structures can be fabricated. Forexample, while the ohmic contacts are described as metallic, othercontacts such as doped polysilicon can be employed. Thus, variousapplications, changes, and modifications may occur to those skilled inthe art without departing from the true spirit and scope of theinvention as defined by the appended claims.

What is claimed is:
 1. A monolithic semiconductor .Iadd.SCR.Iaddend.device comprising:a semiconductor .[.body.]. .Iadd.substrate ofone conductivity type and an epitaxial layer of opposite conductivitytype, said epitaxial layer .Iaddend.having at least one major surface,and .[.a body region adjacent to said surface of one conductivitytype,.]. first and second spaced regions of .[.opposite.]. .Iadd.saidone .Iaddend.conductivity type formed in said .[.body region.]..Iadd.epitaxial layer .Iaddend.and abutting said major surface, thirdand fourth regions of said .[.one conductivity.]. .Iadd.oppositeconductivity .Iaddend.type formed in said first and second regions,respectively, abutting said major surface and defining first and secondchannel regions in said first and second regions, respectively, a layerof insulation on said major surface, a gate electrode formed on saidlayer of insulation and above said first and second channel regions, anohmic contact to said first and third regions, and an ohmic contact tosaid second and fourth regions.Iadd., and .Iaddend. .Iadd.an ohmiccontact to said semiconductor substrate.Iaddend.. .[.2. A monolithicsemiconductor device as defined by claim 1 and further including a fifthregion of said one conductivity type formed in said semiconductor bodybetween and spaced from said first and second regions..].
 3. Amonolithic semiconductor device as defined by claim .[.2.]. .Iadd.1.Iaddend.wherein said one conductivity type is .[.N.]. .Iadd.P.Iaddend.type and said opposite conductivity type is .[.P.]. .Iadd.N.Iaddend.type. .[.4. A monolithic semiconductor device as defined byclaim 2 and including an ohmic contact to said fifth region..]. .[.5. Amonolithic semiconductor device as defined by claim 1 wherein said bodyregion of said semiconductor body comprises an epitaxial layer..].
 6. Amonolithic semiconductor device as defined by claim .[.5.]. .Iadd.1.Iaddend.wherein said semiconductor device is electrically isolated byan isolation region through said epitaxial layer and surrounding saiddevice. . A monolithic semiconductor device as defined by claim 6wherein said isolation region comprises a diffused region.
 8. Amonolithic semiconductor device as defined by claim 6 wherein saidisolation region comprises a dielectric material.
 9. A monolithicsemiconductor device as defined by claim 6 .[.wherein said semiconductorbody includes.]. .Iadd.and including a .Iaddend.plurality of likesemiconductor devices which are spaced and isolated from said one deviceby said isolation region.
 10. A monolithic semiconductor device asdefined by claim 1 wherein .[.said semiconductor body comprises asemiconductor substrate of said opposite conductivity type, said bodyregion comprises an epitaxial layer of said one conductivity type formedon said substrate,.]. said first and second regions are spaced apart bya V-groove formed in said major surface and further including a layer ofinsulation over the surface of said V-groove and .[.a.]. .Iadd.said.Iaddend.gate electrode .Iadd.is .Iaddend.formed over said layer ofinsulation and spaced from said surface of said V-groove. .[.11. Amonolithic semiconductor device as defined by claim 1 and furtherincluding a fifth region of said opposite conductivity type abuttingsaid major surface and spaced from said first region, an insulatinglayer overlying said major surface between said first and fifth regions,and a gate electrode formed on said insulative layer..].
 12. Anelectrical .Iadd.triac .Iaddend.circuit device comprising:a first doublediffused field effect transistor having source, gate, and drain regions,a second double diffused field effect transistor having source, gate,and drain regions, means ohmically connecting said drain regions,contact means for said gate regions, .[.an.]. .Iadd.a first anode.Iaddend.ohmic contact to said source region of said first field effecttransistor, and .[.an.]. .Iadd.a second anode .Iaddend.ohmic contact tosaid source region of said second field effect transistor.Iadd.,.Iaddend. .Iadd.said first and second field effect transistors beingformed in a semiconductor body and said means ohmically connecting saiddrain regions comprises a region of said semiconductor body. .Iaddend..[.13. An electrical circuit device as defined by claim 12 wherein saidfirst and second field effect transistors are formed in a semiconductorbody and said means ohmically connecting said drain regions comprises aregion of said semiconductor body..].
 14. An electrical circuit deviceas defined by claim 12 wherein said source and drain regions are N type,and said channel regions are P type.
 15. An electrical circuit device asdefined by claim 12 wherein said semiconductor body includes anepitaxial layer and said first and second field effect transistors areformed in said epitaxial layer.
 16. An electrical circuit device asdefined by claim 15 and including an isolation region extending throughsaid epitaxial layer and surrounding said first and second field effecttransistors.
 17. A monolithic semiconductor device as defined by claim16 wherein said isolation region comprises a diffused region.
 18. Amonolithic semiconductor device as defined by claim 16 wherein saidisolation region comprises a dielectric material.
 19. A monolithic bodyhaving a plurality of isolated semiconductor regions of one conductivitytype abutting a major surface of said body, each region including anelectrical .Iadd.triac .Iaddend.device comprisingfirst and second spacedregions of opposite conductivity type, third and fourth regions of saidone conductivity type formed in said first and second regions,respectively, and defining first and second channel regions in saidfirst and second regions, respectively, a layer of insulation on thesurface of said semiconductor region, a gate electrode formed on saidlayer of insulation and adjacent to said first and second channelregions, .[.an.]. .Iadd.a first anode .Iaddend.ohmic contact to saidfirst and third regions, and .[.an.]. .Iadd.a second anode.Iaddend.ohmic contact to said second and fourth regions.
 20. Amonolithic body as defined by claim 19 wherein said insulation layercomprises silicon oxide and said monolithic body comprises a siliconsubstrate.
 21. A monolithic body as defined by claim 20 wherein saidmonolithic body further includes an epitaxial layer and said electricaldevice is formed in said epitaxial layer.
 22. A monolithic body asdefined by claim 21 wherein said isolation is provided by diffusedregions through said epitaxial layer of said opposite conductivity type.. A monolithic body as defined by claim 21 wherein said isolation isformed by dielectric material extending through said epitaxial layer.24. A monolithic body as defined by claim 23 wherein said dielectricmaterial is silicon oxide.
 25. A monolithic semiconductor devicecomprising:a semiconductor substrate of one conductivity type, anepitaxial layer of opposite conductivity type, said epitaxial layerhaving a major surface, isolation means extending through said epitaxiallayer and defined at least two isolated regions in said epitaxial layer,one of said isolated regions including a first double diffused fieldeffect transistor having source, gate, and drain regions, a seconddouble diffused field effect transistor having source, gate, and drainregions, means ohmically connecting said drain regions, contact meansfor said gate regions, an ohmic contact to said source region of saidfirst field effect transistor, and an ohmic contact to said sourceregion of said second field effect transistor, another of said isolatedregions including a third field effect transistor having source, gate,and drain regions, and means electrically connecting said source regionof said third transistor and said source region of said secondtransistor, said source region of said first transistor functions as ananode, said connected source regions of said second and third transistorfunction as a cathode, said gate regions of said first and secondtransistors function as an on gate, and said gate of said third fieldeffect transistor functions as an off gate.